Generally speaking, at design of integrated circuits such as LSIs, cell arrangement and inter-cell wiring are performed, and a noise value that may arise in each wire is calculated and checked (see, for example, the Patent Documents 1 and 2 listed below). In cases where a noise value exceeding a limit value is caused, (that is, when a noise value error occurs), cell rearrangement and inter-cell rewiring are performed.
Referring to accompanying drawing FIGS. 21A, 21B, 21C, and 22, a common LSI designing method will be detailed hereinbelow. FIGS. 21A, 21B and 21C are views for describing the hierarchical morphology of LSI design; FIG. 22 is a flow chart indicating common LSI designing procedures.
As shown in FIGS. 21A and 21B, during LSI design, the LSI chip 1 being designed is hierarchically organized into three groups: a chip level, a sub-chip level, and an LSG (Layout Sub Group) level. Cell arrangement and inter-cell wiring are performed either on a sub-chip level or on the lowest layer of the LSG level.
In FIG. 21A, reference character 1a designates a sub chip; reference character 1b, an LSG; reference character 1c, an external I/O area; reference character 1d, custom macro in LSG 1b; reference character 1e, a standard cell in sub chip 1a (or LSG 1b).
Here, custom macro 1d is huge in size as compared to standard cell 1e and represents a large cell (hard macro, custom macro, IP, hereinafter called custom macro in this description) such as primitive RAM, ROM and RF.
Such custom macro 1d is treated similarly to standard cell 1e and is arranged along with standard cells 1e on sub chip 1a (or LSG 1b), as shown in FIG. 21C. Wiring by means of wires/vias 1g is performed on arranged custom macros 1d, standard cells 1e, and module pins 1f. 
As wiring by means of wires/vias 1g as described above, custom macro 1d is treated as a black box. For custom macro 1d, at least information about terminals of custom macro 1d (coordinate information representing terminal positions and layer information representing layers where the terminals exist, hereinafter called terminal information) and information about wiring forbidden areas each formed on or inside the custom macro 1d (coordinate information representing areas and layer information representing layers where the areas exist, hereinafter called wiring forbidden information) are provided to the designer or the like. These pieces of information are determined by a designer or the like at a division of custom macro 1d design during internal design of the custom macro 1d, and are provided in the form of a library such as a GDS or a verilog. The terminal positions and the wiring forbidden areas are corresponding to areas at which terminals, wires (wires/vias) and internal elements (gates and cells) exist.
After receipt of these pieces of information, another designer performs wiring of wires/vias 1g between terminals of custom macros 1d and terminals of standard cells 1e or module pins 1f based on the terminal information, and at the same time avoids the wiring using the wires/vias 1g from the wiring forbidden areas based on the wiring forbidden information as shown in FIG. 21C.
Such an LSI chip 1 is designed, following the procedures (steps S101 through S111) of FIG. 22. RTL (Register Transfer Level) design is performed first (step S101), and logic synthesis (step S102) and floor planning and layer division (here, division of LSI chip 1 into sub chips 1a) (step S103) are then performed. After that, designing of each sub chip 1a obtained by the layer division is performed (step S104).
Design of each sub chip 1a includes procedural steps of performing arrangement and inter-cell wiring on standard cells 1e and custom macros (large cells) 1d (step S105) in accordance with the result of floor planning in step S103, and terminal information and wiring forbidden information of custom macros 1d, and performing a static noise check on the result obtained by the cell-arrangement and the inter-cell wiring (step S106).
In the static noise checking, a noise value is calculated as a degree at which at least one affecting wire (aggressor), which is a wire running in parallel with an object wire (victim) to be checked that is to be checked, induces noise onto the victim, and it is evaluated whether or not the noise value exceeds a limit value (step S107). If the noise value exceeds the limit value, it is decided that a noise value error has occurred (YES route of step S107), the process returns to step S105, and the same procedures (steps S105 through S107) are repeated until step S107 makes a NO decision. On the other hand, if the noise value is equal to or smaller than the limit value, it is decided that no noise value error occurs (NO route of step S107). The above procedure (steps S105-S107) is performed for each sub chip 1a. 
During the above static noise check, each custom macro 1d is regarded as a black box having unknown internal cell arrangement and unknown inter-cell wiring. For this reason, the static noise check is not performed on internal wires of custom macro 1d in relation to wires/vias 1g each wired on or inside custom macro 1d as shown in FIG. 21C.
After performing cell arrangement and inter-cell wiring on all the sub chips 1a, if it is decided that no noise value error occurs on the sub chips 1a, the entire LSI chip 1 is designed by combining the results of designing of all the sub chips 1a (step S108). Subsequently, the static noise check is performed on the result of the design of the entire LSI chip 1 in the same manner as performed in step S106 (step S109).
In other words, a noise value is calculated as a degree at which at least one aggressor, which is a wire running in parallel with a victim wire that is to be checked, induces noise onto the victim, and it is evaluated whether or not the noise value exceeds a limit value (step S110). If the noise value exceeds the limit value, it is decided that a noise value error has occurred (YES route of step S110), the process returns to step S104, and the same procedures (steps S104 through S110) are repeated until step S110 makes a NO decision. On the other hand, if the noise value is equal to or smaller than the limit value, it is decided that no noise value error occurs (NO route of step S110), and manufacture data for the LSI chip 1 is produced (step S111) based on the cell arrangement and the inter-cell wiring, and the design of the LSI chip 1 is completed.
Prior to the static noise checks (at steps S106 and S109), a static timing analysis may be performed on the result of the cell arrangement and the inter-cell wiring of each sub chip 1a or on the result of the design of the entire LSI chip 1, however not shown in FIG. 22. If the static timing analysis finds a problem (error such as signal delay/racing) in timing, the process returns to step S105 or S104, and cell arrangement and inter-cell wiring or design of sub chip 1a are performed once again.
Patent Document 1: Japanese Patent Application Laid-Open (KOKAI) No. 2001-217315
Patent Document 2: Japanese Patent Application Laid-Open (KOKAI) No. HEI 5-314220
In order that the internal wires of custom macro 1d and wires/vias 1g among custom macro 1d, standard cell 1e and module pin 1f induce no noise onto each other, it is suggested as one solution that wiring with the wires/vias 1g is performed avoiding the portion on, in and close to the custom macro 1d. However, since custom macro 1d is huge in size as compared to standard cell 1e, custom macros 1d occupy the area of LSI chip 1 at a high ratio. Wiring with wires/vias 1g avoiding the portion on, in and close to the custom macro 1d cannot improve the integration and additionally may make the layout design difficult.
Accordingly, wiring with wires/vias 1g is practically performed considering the wiring forbidden areas in, on, and close to custom macro 1d as shown in FIG. 21C, but has a high possibility of a noise value error occurring between an internal wire (inter-element wire) of custom macro 1d and wire/via 1g. As described above, since custom macro 1d is however treated as a black box inside wires of which are totally unknown and therefore a static noise check is not performed on wires (internal wires) in relation to wires/vias 1g in and on custom macro 1d, as shown in FIG. 21C, it is impossible to grasp a degree of influence of the internal wires of custom macro 1d on wires/vias 1g in and on the custom macro 1d during a layout design. As a solution to the problem, it has been proposed a technique of spuriously treating internal wires of custom macro 1d of a black box as an object of static noise check and consequently performing a static noise check between internal wires of custom macro 1d and wires/vias 1g during a layout design.